The integration function, or integral, is a mathematical function that is well known in the art. Briefly, an integral is a mathematical object that can be interpreted as an area or a generalization of area. If a signal is plotted as a curve, the integral of the signal is the area under the curve. An integrator is a device that integrates a signal present at its input and produces an integrated version of the input signal at its output.
Integrators are often used to improve the quality of electronic signals prior to further processing steps. By way of example FIG. 1 illustrates a signal source 100 and a signal processing chain that consists of integrator 110, analog to digital converter (ADC) 120 and DSP 130. In FIG. 1 analog to digital conversion implemented by ADC 120 and digital signal processing steps using DSP 130 are further processing steps that rely on high quality integrator output.
Signal source 100 generates a signal. By way of example, signal source 100 could be a sensor such as a strain gage, a fuel flow sensor, a light intensity sensor or any other type of device that generates a signal in response to external stimuli. Signal source 100 is often, but not always, physically removed from the circuit assembly containing integrator 110, analog to digital converter (ADC) 120 and DSP 130.
The quality of the signal is improved by integrator 110 which integrates the signal VIN. FIG. 2 illustrates the nature of the signal improvement. Waveform 200 is the combination of a constant value signal generated by signal source 100 and additive noise that corrupts the constant value signal. Waveform 210 is the integrator output generated in response to input signal waveform 200. It is readily observed that signal fluctuations caused by the additive noise are decreased by operation of the integrator, as illustrated by waveform 210.
The output of integrator 110, VOUT, is input to ADC 120. ADC 120 performs the analog to digital conversion function. The analog to digital conversion function is well known in the art. The analog signal VOUT present at ADC 120 input is converted into signal VD that can take one of a set of discrete levels.
FIG. 3 illustrates two ADC 120 input signals, 300 and 310, and corresponding ADC 320 output levels. Signals 300 and 310 are integrator 110 outputs in response to input signals of unequal power. Signal 300 is an integrator 110 output in response to a higher power input signal. Signal 310 is an integrator 110 output in response to a low power input signal.
Vertical bar 320 represents the ADC conversion characteristic. An analog ADC 120 input signal value will be mapped into one of a finite set of discrete signal output values. The horizontal tic marks on bar 320 illustrate the set of discrete ADC 120 output values. ADC 120 is a five-bit device as illustrated here and it converts input signals into one of 32 discrete values. The discrete values span the range of 0 to 31 or 00000 to 11111 in binary representation. There are 32 corresponding tic marks on bar 320, each one corresponding to a specific analog voltage value.
In FIG. 3 ADC 120 samples and converts the signal present at its input at time T=100. Signal 300 reaches a value of five volts at time T=100 and it is converted to digital value 31 which is the highest possible output code of ADC 120. Signal 310 reaches a value of approximately 0.5 volts and it is converted to digital value three which is a relatively low output code of ADC 120. An ADC input signal value that does not correspond exactly to one of the tick marks on bar 320 will be rounded-off to the value of the nearest tick-mark.
The conversion error introduced by the rounding-off process is represented as quantization noise. The quantization error and associated quantization noise introduced by ADC is well known to one versed in the art. The round-off errors are proportionally more significant for lower value signals and less significant for higher value signals. Signal 300 will be affected less by quantization noise than signal 310. In other words the signal to quantization noise ratio of signal 300 will be higher than the signal to quantization noise ration of signal 310.
Signal to quantization noise ratio is a measure of signal degradation that negatively affects system performance. The minimum acceptable signal to quantization noise ratio is a design parameter and for that reason the minimum number of levels or equivalently the minimum number of bits of ADC 120 is a system design requirement.
Another kind of noise that degrades signal quality is additive thermal noise. For a given power of the thermal noise that corrupts ADC 120 input signals, differences in input signal levels smaller than some value cannot be reliable resolved. FIG. 4 illustrates this limitation. FIG. 4 shows the output of integrator 110 due to two different signals. The signals are corrupted by additive thermal noise. The signals have a constant value for the duration of the integration process and the integrator inputs consist of the constant signal values and additive thermal noise. In both cases the output value of interest of integrator 110 occur at time T=100 when the integration process ends.
In FIG. 4A signal 520 is the input to the integrator due to signal #1 which has a constant value of 1.5 volts and signal 530 is the input to the integrator due to signal #2 which has a constant value of 1 volt. Signal 500 is the integrator output due to input signal 520 and signal 510 is the integrator output due to input signal 530. Integrator output signals 500 and 510 cannot be reliably distinguished from one another at time T=100 due to excessive amounts of residual additive noise. This exemplifies that under these noise conditions the minimum required difference in signal levels at the output of integrator 110 should be in excess of the difference between signal #1 and signal #2 which is 0.5 volts. Smaller signal level differences cannot reliable resolved using integrator 110.
In FIG. 4B signal 560 is the input to integrator 110 due to signal #3 which has a constant value of 2.5 volts. Signal 570 is the input to integrator 110 due to signal #4 which has a constant value of 1 volt. Signal 540 is the integrator 110 output due to input signal 560. Signal 550 is the integrator 110 output due to input signal 570. Integrator output signals 540 and 550 can be reliably distinguished from one another at time T=100. This indicates that two signal levels can be reliably resolved if the difference in signal levels at the output of integrator 110 equals the difference between signal #3 and signal #4 which is 1.5 volts.
Signal source 100 will generate a signal of sufficient maximum amplitude to insure that thermal noise effects are limited and do not significantly degrade system performance. This implies that at times the output of integrator 110 might be required to have a value larger than the available power supply voltage.
FIG. 5 illustrates a simple integrator circuit. The integrator input signal is generated by signal source 1000 and corrupted by noise source 1010. The signal and noise are added by adder 1020. This is a diagrammatic representation of signal and additive noise. In real electronic circuits the electronic components intrinsically generate noise and the addition of noise to the signal occurs through inductive and other effects intrinsic to the physical component and system design and layout.
Capacitor 1040 is a simple integrator. The input to the integrator is the output of adder 1020. Capacitor 1040 is reset by switch 1050 which is in the closed position prior to starting the integration process and resets the integrator. At the start of the integration process switch 1050 opens and the voltage across capacitor 1040 begins to change in response to the input signal originating from the output of adder 1020. At the end of the integration process switch 1030 closes and integrator output 1060, VOUT, is sampled. FIG. 4 is an illustrative diagram. The implementation of other similar integrators with identical functionality is well known and obvious to one skilled in the art.
Integrator output 1060, VOUT, cannot in general exceed the upper limit imposed by the available power supply voltage. Power supply voltages are decreasing in state-of-the-art equipment due to stringent power consumption requirements.
The required output voltage range of integrator 110 and input voltage range of ADC 120 can be in excess of the available system power supply voltage. By way of example this can occur when the output range of signal generator 100 is close to or larger than the available system power supply voltage. When the required output voltage range of integrator 110 is in excess of the available system power supply voltage the integrator output enters into saturation.
Integrator output saturation occurs when the output voltage reaches its maximum value, here the available power supply voltage, and is unable to further increase its value in response to the input signal stimulus. Signal saturation causes system performance degradation. This condition will cause saturation when using conventional integrators, a simplified version of which is illustrated in FIG. 4. Solutions to this problem have been published. The feature the published solutions have in common is the monitoring of the integrator output to detect the onset of saturation condition at which time the integrator is discharged and the event is recorded. By way of example of such solutions Mazzucco discloses in U.S. Pat. No. 6,407,610 methods to prevent saturation of the integrator output. The prevention methods consist of sensing the onset of saturation and resetting (discharging) the integrator or changing the direction of integration when the onset of saturation is sensed. An external circuit records all such events. At the end of the integration period the effective full range of the integration is reconstructed from the number of recorded reset events and from the final integrator output voltage.
This class of solutions is difficult to implement efficiently in integrated circuits (ICs) due to accuracy requirements of analog components and non-standard analog implementations. The implementation of accurate comparators that operate in a noisy environment near the power supply voltage, where integrator outputs begin to saturate, is a difficult undertaking that consumes excessive power, an undesirable operational feature. Analog IC designs are difficult and time consuming to implement. It is advantageous to use standard building blocks that have been fully debugged and optimized for size, power consumption and performance. The class of published solutions does not meet this requirement.